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preliminary data sheet SD1200 analog-interface xga/sxga tft lcd display controller september 1998 smartasic, inc.
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 2 SD1200 preliminary data sheet prsd-1200-a september 1998 document revisions date prsd-1200-a first preliminary datasheet september 1998 copyrigh t 1998, smartasic, inc. all right reserved smartasic, inc. reserves the right to change or modify the information contained herein without notice. it is the customer ? s responsibility to ensure he/she has the most recent revision of the user guide. smartasic, inc. makes no warranty for the use of its products and bears no responsibility for any error or omissions, which may appear in this document.
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 3 SD1200 analog-interface xga/sxga tft lcd display controller features highly integrated analog interface xga/sxga tft lcd display controller handle both 24-bit and 48-bit sampled rgb input up to sxga (1280x1024) @ 85hz support various pc graphics cards drive 48-bit digital rgb output up to sxga (1280x1024) @ 75hz support various tft lcd panels truly ? plug and display ? no special driver running on pc implement proprietary smartdisplay technology for - input mode detection and auto calibration - output image scaling and interpolation - 16.7 million true color support for 6 bit panel - robust detection and handling of invalid input modes advanced input mode detection and auto calibration - input refresh rate detection - input format detection - input sync polarity detection - image expansion - input frequency detection - optimal sampling clock phase calibration advanced image scaling and interpolation with - automatic image centering - automatic image expansion in both horizontal and vertical directions - programmable horizontal and vertical expansion ratio - programmable horizontal and vertical interpolation algorithm true color support for 6 bit panel - proprietary dithering based on both intensity and spatial information - optional frame modulation robust handling of invalid input conditions - detect no input signal - detect input signal beyond specified acceptable range - output status indicators - generate output signal even when no input signal support multiple tft lcd panels - programmable output timing parameters to match specifications of various tft lcd panels - support power on/off sequence - output signal is synchronized with the input signal with the same frame rate low-cost system solution - no external frame buffer required - 2-wire i 2 c serial interface for eeprom and cpu - programmable osd mixer - direct interface to external adc ? s and pll ? s - 160 pin pqfp package - 5.0v and 3.3v supply
1. overview the SD1200 is an ic designed for analog-interface xga/sxga tft lcd monitors. an analog-interface lcd monitor takes analog rgb signals from a graphic card of a personal computer, the exact same input interface as a conventional crt monitor. this feature makes analog-interface lcd monitor a true replacement of a conventional crt monitor. the analog input rgb signals are first sampled by six channels of 8-bit a/d converters, and the 48-bit rgb data are then fed into the SD1200. the SD1200 is capable of performing automatic detection of the display resolution and timing of input signals generated from various pc graphic cards. no special driver is required for the timing detection, nor does any manual adjustment. the SD1200 then automatically scales the input image to fill the full screen of the lcd monitor. the SD1200 can interface with tft lcd panels from various manufacturers by generating 48-bit rgb signal to the lcd panel based upon the timing parameters saved in the eeprom. the SD1200 provides two distinguished features to the tft lcd monitor solution. the first one is ? plug-and-play ? , and the second one is ? cost-effective system solution ? . to be truly plug-and-display, the SD1200 performs automatic input mode detection and auto phase calibration, so that the lcd monitor can ensure the a/d converters ? sample clock to be precisely synchronized with the input video data, and to preserve the highest image bandwidth for the highest image quality. furthermore, the SD1200 can generate output video even when the input signal is beyond the specifications, or no input signal is fed. for ? cost-effective system solution ? , the SD1200 implements many system support features such as osd mixer, error status indicators, 2-wire i 2 c serial interface for both eeprom and host cpu interface, and low-cost ic package. another important contributing factor is that SD1200 does not require external frame buffer memory for the automatic image scaling and synchronization. the SD1200 can handle input signal up to sxga (1280x1024) resolution at 75hz refresh rate, and produce output signal at sxga resolution at 75hz refresh rate (subject to the limitation of lcd panel).
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 5 figure 1 shows the block diagram of the SD1200 as well as the connections of important system components around the SD1200. figure 1: SD1200 functional block diagram input mode detection & auto calibration buffer memory scaling interpolation dithering osd mixer write control read control cpu interface e 2 rom interface adc phase control input pll cpu output pll e 2 prom tft lcd monitor
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 6 2. pin description figure 2: SD1200 package diagram smartasic SD1200 1 40 41 80 120 81 160 12
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 7 able 1: SD1200 pin description (sorted by pin number) symbol pin number voltage i/o description b_in06 1 5 i input color blue b_in07 2 5 i input color blue b_in10 3 5 i input color blue b_in11 4 5 i input color blue b_in12 5 5 i input color blue b_in13 6 5 i input color blue data_sel 7 5 i select input odd/even data b_in14 8 5 i input color blue b_in15 9 5 i input color blue b_in16 10 5 i input color blue b_in17 11 5 i input color blue gnd 12 ground hsync_i 13 5 i input hsync (active low) vsync_i 14 5 i input vsync (active low) mode_in0 15 5 i input mode select 1: double 24 bit rgb 0: single 24 bit rgb mode_in1 16 5 i device id bit 4 for cpu interface (pull high internally) vdd_5v 17 5 +5v power supply mode_in2 18 5 i device id bit 5 for cpu interface (pull high internally) mode_in3 19 5 i device id bit 6 for cpu interface (pull high internally) rom_scl 20 5 o scl in i 2 c for eeprom interface rom_sda 21 5 i/o sda in i 2 c for eeprom interface gnd 22 ground cpu_scl 23 5 i scl in i 2 c for cpu interface cpu_sda 24 5 i/o sda in i 2 c for cpu interface pwm_ctl 25 5 o pwm control signal (detail description in pwm operation section) clk_1m 26 5 i free running clock (default: 1mhz) vdd_5v 27 5 +5v power supply clk_1m_o 28 5 o feedback of free running clock reset_b 29 5 i system reset ( active low) r_osd 30 5 i osd color red g_osd 31 5 i osd color green b_osd 32 5 i osd color blue en_osd 33 5 i osd mixer enable =0, no osd output =1,r_out[7:0]= {r_osd repeat 8 times} g_out[7:0]= {g_osd repeat 8 times } b_out[7:0]= {b_osd repeat 8 times } scan_en 34 5 1 manufacturing test pin (nc) test_en 35 5 i manufacturing test pin (nc) test_h 36 5 i manufacturing test pin (nc) tst_done 37 5 o manufacturing test pin (nc) fail_h 38 5 o manufacturing test pin (nc) hsync_x 39 5 o default hsync generated by asic (active
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 8 low) vsync_x 40 5 o default vsync generated by asic (active low) gnd 41 ground fclk0 42 5 o input pll feedback clock vclk0 43 5 i input pll output clock fclk1 44 5 o output pll feedback clock vclk1 45 5 i output pll output clock hsync_o 46 3.3 o output hsync vsync_o 47 3.3 o output vsync dclk_out 48 3.3 o output clock to control panel de_out 49 3.3 o output display enable for panel (active high) vdd_5v 50 5 +5v power supply r_out0_e 51 3.3 o output color red even pixel r_out1_e 52 3.3 o output color red even pixel r_out2_e 53 3.3 o output color red even pixel r_out3_e 54 3.3 o output color red even pixel vdd_3.3v 55 3.3 +3.3v power supply r_out4_e 56 3.3 o output color red even pixel r_out5_e 57 3.3 o output color red even pixel r_out6_e 58 3.3 o output color red even pixel r_out7_e 59 3.3 o output color red even pixel gnd 60 ground r_out0_o 61 3.3 o output color red odd pixel r_out1_o 62 3.3 o output color red odd pixel r_out2_o 63 3.3 o output color red odd pixel r_out3_o 64 3.3 o output color red odd pixel vdd_5v 65 5 +5v power supply r_out4_o 66 3.3 o output color red odd pixel r_out5_o 67 3.3 o output color red odd pixel r_out6_o 68 3.3 o output color red odd pixel r_out7_o 69 3.3 o output color red odd pixel gnd 70 ground g_out0_e 71 3.3 o output color green even pixel g_out1_e 72 3.3 o output color green even pixel g_out2_e 73 3.3 o output color green even pixel g_out3_e 74 3.3 o output color green even pixel g_out4_e 75 3.3 o output color green even pixel vdd_3.3v 76 3.3 +3.3v power supply g_out5_e 77 3.3 o output color green even pixel g_out6_e 78 3.3 o output color green even pixel g_out7_e 79 3.3 o output color green even pixel gnd 80 ground g_out0_o 81 3.3 o output color green odd pixel g_out1_o 82 3.3 o output color green odd pixel g_out2_o 83 3.3 o output color green odd pixel g_out3_o 84 3.3 o output color green odd pixel vdd_5v 85 5 +5v power supply g_out4_o 86 3.3 o output color green odd pixel g_out5_o 87 3.3 o output color green odd pixel g_out6_o 88 3.3 o output color green odd pixel g_out7_o 89 3.3 o output color green odd pixel
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 9 gnd 90 ground b_out0_e 91 3.3 o output color blue even pixel b_out1_e 92 3.3 o output color blue even pixel b_out2_e 93 3.3 o output color blue even pixel b_out3_e 94 3.3 o output color blue even pixel b_out4_e 95 3.3 o output color blue even pixel b_out5_e 96 3.3 o output color blue even pixel b_out6_e 97 3.3 o output color blue even pixel vdd_3.3v 98 3.3 +3.3v power supply b_out7_e 99 3.3 o output color blue even pixel gnd 100 ground b_out0_o 101 3.3 o output color blue odd pixel b_out1_o 102 3.3 o output color blue odd pixel b_out2_o 103 3.3 o output color blue odd pixel b_out3_o 104 3.3 o output color blue odd pixel vdd_5v 105 5 +5v power supply b_out4_o 106 3.3 o output color blue odd pixel b_out5_o 107 3.3 o output color blue odd pixel b_out6_o 108 3.3 o output color blue odd pixel b_out7_o 109 3.3 o output color blue odd pixel gnd 110 ground r_in00 111 5 i input color red r_in01 112 5 i input color red r_in02 113 5 i input color red r_in03 114 5 i input color red vdd_5v 115 5 +5v power supply r_in04 116 5 i input color red r_in05 117 5 i input color red r_in06 118 5 i input color red r_in07 119 5 i input color red gnd 120 ground r_in10 121 5 i input color red r_in11 122 5 i input color red r_in12 123 5 i input color red r_in13 124 5 i input color red vdd_5v 125 5 +5v power supply r_in14 126 5 i input color red r_in15 127 5 i input color red r_in16 128 5 i input color red r_in17 129 5 i input color red gnd 130 ground g_in00 131 5 i input color green g_in01 132 5 i input color green g_in02 133 5 i input color green g_in03 134 5 i input color green vdd_5v 135 5 +5v power supply g_in04 136 5 i input color green g_in05 137 5 i input color green adc_clk0 138 5 o sample clock for adc 0 g_in06 139 5 i input color green g_in07 140 5 i input color green gnd 141 ground
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 10 g_in10 142 5 i input color green g_in11 143 5 i input color green adc_clk1 144 5 o sample clock for adc 1 g_in12 145 5 i input color green g_in13 146 5 i input color green vdd_5v 147 5 +5v power supply g_in14 148 5 i input color green g_in15 149 5 i input color green g_in16 150 5 i input color green g_in17 151 5 i input color green gnd 152 ground b_in00 153 5 i input color blue b_in01 154 5 i input color blue b_in02 155 5 i input color blue b_in03 156 5 i input color blue vdd_5v 157 5 +5v power supply b_in04 158 5 i input color blue b_in05 159 5 i input color blue gnd 160 ground
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 11 table 2: SD1200 pin description (sorted by function) symbol pin number voltage i/o description r_in00 111 5 i input color red r_in01 112 5 i input color red r_in02 113 5 i input color red r_in03 114 5 i input color red r_in04 116 5 i input color red r_in05 117 5 i input color red r_in06 118 5 i input color red r_in07 119 5 i input color red r_in10 121 5 i input color red r_in11 122 5 i input color red r_in12 123 5 i input color red r_in13 124 5 i input color red r_in14 126 5 i input color red r_in15 127 5 i input color red r_in16 128 5 i input color red r_in17 129 5 i input color red g_in00 131 5 i input color green g_in01 132 5 i input color green g_in02 133 5 i input color green g_in03 134 5 i input color green g_in04 136 5 i input color green g_in05 137 5 i input color green g_in06 139 5 i input color green g_in07 140 5 i input color green g_in10 142 5 i input color green g_in11 143 5 i input color green g_in12 145 5 i input color green g_in13 146 5 i input color green g_in14 148 5 i input color green g_in15 149 5 i input color green g_in16 150 5 i input color green g_in17 151 5 i input color green b_in00 153 5 i input color blue b_in01 154 5 i input color blue b_in02 155 5 i input color blue b_in03 156 5 i input color blue b_in04 158 5 i input color blue b_in05 159 5 i input color blue b_in06 1 5 i input color blue b_in07 2 5 i input color blue b_in10 3 5 i input color blue b_in11 4 5 i input color blue b_in12 5 5 i input color blue b_in13 6 5 i input color blue b_in14 8 5 i input color blue b_in15 9 5 i input color blue b_in16 10 5 i input color blue b_in17 11 5 i input color blue
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 12 hsync_i 13 5 i input hsync (active low) vsync_i 14 5 i input vsync (active low) mode_in0 15 5 i input mode select 1: double 24 bit rgb 0: single 24 bit rgb mode_in1 16 5 i device id bit 4 for cpu interface (pull high internally) mode_in2 18 5 i device id bit 5 for cpu interface (pull high internally) mode_in3 19 5 i device id bit 6 for cpu interface (pull high internally) adc_clk0 138 5 o sample clock for adc 0 adc_clk1 144 5 o sample clock for adc 1 r_out0_e 51 3.3 o output color red even pixel r_out1_e 52 3.3 o output color red even pixel r_out2_e 53 3.3 o output color red even pixel r_out3_e 54 3.3 o output color red even pixel r_out4_e 56 3.3 o output color red even pixel r_out5_e 57 3.3 o output color red even pixel r_out6_e 58 3.3 o output color red even pixel r_out7_e 59 3.3 o output color red even pixel r_out0_o 61 3.3 o output color red odd pixel r_out1_o 62 3.3 o output color red odd pixel r_out2_o 63 3.3 o output color red odd pixel r_out3_o 64 3.3 o output color red odd pixel r_out4_o 66 3.3 o output color red odd pixel r_out5_o 67 3.3 o output color red odd pixel r_out6_o 68 3.3 o output color red odd pixel r_out7_o 69 3.3 o output color red odd pixel g_out0_e 71 3.3 o output color green even pixel g_out1_e 72 3.3 o output color green even pixel g_out2_e 73 3.3 o output color green even pixel g_out3_e 74 3.3 o output color green even pixel g_out4_e 75 3.3 o output color green even pixel g_out5_e 77 3.3 o output color green even pixel g_out6_e 78 3.3 o output color green even pixel g_out7_e 79 3.3 o output color green even pixel g_out0_o 81 3.3 o output color green odd pixel g_out1_o 82 3.3 o output color green odd pixel g_out2_o 83 3.3 o output color green odd pixel g_out3_o 84 3.3 o output color green odd pixel g_out4_o 86 3.3 o output color green odd pixel g_out5_o 87 3.3 o output color green odd pixel g_out6_o 88 3.3 o output color green odd pixel g_out7_o 89 3.3 o output color green odd pixel b_out0_e 91 3.3 o output color blue even pixel b_out1_e 92 3.3 o output color blue even pixel b_out2_e 93 3.3 o output color blue even pixel
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 13 b_out3_e 94 3.3 o output color blue even pixel b_out4_e 95 3.3 o output color blue even pixel b_out5_e 96 3.3 o output color blue even pixel b_out6_e 97 3.3 o output color blue even pixel b_out7_e 99 3.3 o output color blue even pixel b_out0_o 101 3.3 o output color blue odd pixel b_out1_o 102 3.3 o output color blue odd pixel b_out2_o 103 3.3 o output color blue odd pixel b_out3_o 104 3.3 o output color blue odd pixel b_out4_o 106 3.3 o output color blue odd pixel b_out5_o 107 3.3 o output color blue odd pixel b_out6_o 108 3.3 o output color blue odd pixel b_out7_o 109 3.3 o output color blue odd pixel hsync_o 46 3.3 o output hsync vsync_o 47 3.3 o output vsync dclk_out 48 3.3 o output clock to control panel de_out 49 3.3 o output display enable for panel (active high) fclk0 42 5 o input pll feedback clock vclk0 43 5 i input pll output clock fclk1 44 5 o output pll feedback clock vclk1 45 5 i output pll output clock rom_scl 20 5 o scl in i 2 c for eeprom interface rom_sda 21 5 i/o sda in i 2 c for eeprom interface cpu_scl 23 5 i scl in i 2 c for cpu interface cpu_sda 24 5 i/o sda in i 2 c for cpu interface pwm_ctl 25 5 o pwm control signal (detail description in pwm operation section) clk_1m 26 5 i free running clock (default: 1mhz) clk_1m_o 28 5 o feedback of free running clock reset_b 29 5 i system reset ( active low) hsync_x 39 5 o default hsync generated by asic (active low) vsync_x 40 5 o default vsync generated by asic (active low) r_osd 30 5 i osd color red g_osd 31 5 i osd color green b_osd 32 5 i osd color blue en_osd 33 5 i osd mixer enable =0, no osd output =1,r_out[7:0]= {r_osd repeat 8 times} g_out[7:0]= {g_osd repeat 8 times } b_out[7:0]= {b_osd repeat 8 times } scan_en 34 5 1 manufacturing test pin (nc) test_h 36 5 i manufacturing test pin (nc)
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 14 fail_h 38 5 o manufacturing test pin (nc) tst_done 37 5 o manufacturing test pin (nc) test_en 35 5 i manufacturing test pin (nc) data_sel 7 5 i select input odd/even data vdd_5v 17 5 +5v power supply vdd_5v 27 5 +5v power supply vdd_5v 50 5 +5v power supply vdd_5v 65 5 +5v power supply vdd_5v 85 5 +5v power supply vdd_5v 105 5 +5v power supply vdd_5v 115 5 +5v power supply vdd_5v 125 5 +5v power supply vdd_5v 135 5 +5v power supply vdd_5v 147 5 +5v power supply vdd_5v 157 5 +5v power supply vdd_3.3v 55 3.3 +3.3v power supply vdd_3.3v 76 3.3 +3.3v power supply vdd_3.3v 98 3.3 +3.3v power supply gnd 12 ground gnd 22 ground gnd 41 ground gnd 60 ground gnd 70 ground gnd 80 ground gnd 90 ground gnd 100 ground gnd 110 ground gnd 120 ground gnd 130 ground gnd 141 ground gnd 152 ground gnd 160 ground
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 15 3. functional description the SD1200 has the following major function blocks: 1. input mode detection & auto calibration block 2. buffer memory and read/write control block 3. image scaling, interpolation and dithering block 4. osd mixer and lcd interface block 5. eeprom interface block 6. cpu interface block the following sections will describe the functionality of these blocks. 3.1. input mode detection & auto calibration block 3.1.1. supported input modes the SD1200 accepts seven different input video modes: 640 x 350 640 x 400 720 x 400 640 x 480 (vga) 800 x 600 (svga) 1024 x 768 (xga) 1280 x 1024 (sxga) there is no frame rate restriction on the input modes. however, since the output signal is synchronized with the input signal at the same refresh rate. the input refresh rate has to be within the acceptable range of the lcd panel. 3.1.2. input mode detection the SD1200 can automatically detect the mode of the input signal without any user adjustment or driver running on the pc host or external cpu. this block
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 16 automatically detects polarity of input synchronization and the sizes of back porch, valid data window and the synchronization pulse width in both vertical and horizontal directions. the size information is then used not only to decide the input resolution, to generate the frequency divider for the input pll, to lock the pll output clock with hsync, but also to automatically scale the image to full screen, and to synchronize the output signal with the input signal. the detection logic is always active to automatically detect any changes to the input mode. users can manually change the input mode information at run time through the cpu interface. detail operation of the cpu interface is described in section. ? cpu interface ? . 3.1.3. auto calibration the SD1200 can automatically calibrate the phase of the sample clock in order to preserve the bandwidth of input signal and get the best quality. the SD1200 implements a proprietary image quality function. during auto-calibration process, the SD1200 continues search for the best phase to optimize the image quality. the output image may display some jitter and blurring during the auto-calibration process, and the image will become crisp and sharp once the optimum phase is found. user can change the sampling clock phase value by the external cpu. detail operation of the cpu interface is described in section. ? cpu interface ? . the auto calibration process can be delayed and even disabled by the external cpu if system designer wants to have his/her own implementation. 3.1.4. pwm operation the SD1200 implements a very unique algorithm to adjust the phase of the a/d converter ? s sampling clock. an external delay circuitry is required to compliment the SD1200 for the auto-calibration process. the SD1200 generates a pulse-width modulated (pwm) signal to the external delay circuitry. the delay circuitry should insert a certain amount of time delay synchronization pulse based upon the width of the pwm signal. a brief circuit diagram for the pwm is shown in figure 3. the pwm signal from the SD1200 is a periodical signal with a period that is 511
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 17 times of the period of the free-running clock connected to the pin ? clk_1m ? . system manufacturers may select any frequency for the free running clock. the default clock frequency is 1mhz. system manufacturers also decide the unit delay for the external delay circuitry. the delay information is stored in the eeprom. when the SD1200 wants to delay the synchronization pulse for n units of delay, it will output the pwm with the high time equal to (n * the period of the free-running clock), and with low time equal to (511-n)* the period of the free-running clock. when n=511, the pwm signal stays high all the time, and when n=0, the pwm signal is always low. figure 3: SD1200 pwm circuitry block diagram 3.1.5. free running clock as described in previous section, a free-running clock is needed for the SD1200. this clock is used for many of the SD1200 ? s internal operations. pwm operation is one of them. system manufacturers can select the frequency of the free-running clock, and the default clock frequency is 1mhz. system manufacturer can use an oscillator to generate the free-running clock, and feed that clock directly to the pin ? clk_1m ? , or use a crystal connecting to ? clk_1m ? and ? clk_1m_o ? . SD1200 pwm delay circuitry synchronization pulse pll ref_clk
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 18 3.2. buffer memory and read/write control block the SD1200 uses internal buffer memory to store a portion of the input image for image scaling and output synchronization. no external memory buffer is needed for the SD1200. the write control logic ensures the input data are stored into the right area of the buffer memory, and the read control logic is responsible to fetch the data from the buffer memory from the correct area and at the correct timing sequence. with the precise timing control of the write and read logic, the output image is appropriately scaled to the full screen, and the output signal is perfectly synchronized with the input signals. 3.3. image scaling, interpolation and dithering block the SD1200 supports both automatic image scaling and interpolation. 3.3.1. image scaling the SD1200 supports several different input modes, and the input image may have different sizes. it is essential to support automatic image scaling so that the input image is always displayed to the full screen regardless the input mode. the SD1200 scale the images in both horizontal and vertical directions. it calculates the correct scaling ratio for both directions based upon the lcd panel resolution, and the input mode and timing information produced by the ? input mode detection & auto calibration ? block. the scaling ratio is re-adjusted whenever a different input mode is detected. the ratio is then fed to the buffer memory read control logic to fetch the image data with the right sequence and timing. some of the image data may be read more than once to achieve scaling effect. 3.3.2. image interpolation the SD1200 supports image interpolation to achieve better image quality. a basic image scaling algorithm replicates the input images to achieve the scaling effect. the replication scheme usually results in a poor image quality. the SD1200 implements both linear interpolation and a proprietary interpolation algorithm. through external micro-controller, users can chose among different interpolation algorithm.
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 19 3.3.3. dithering the SD1200 supports 16.7 million true colors for 6-bit panel. two dithering algorithms are implemented and again users can chose between them through the external micro-controller. 3.4. osd mixer and lcd interface at the output stage, the SD1200 performs the osd mixer function, and then generates 24-bit rgb signal to the lcd panel with the correct timing. 3.4.1. osd mixer in the osd mixer block, the SD1200 mixes the normal output rgb signal with the osd signal. the osd output data is generated based on the ? r_osd ? , ? g_osd ? and ? b_osd ? pins as well as the ? osd intensity ? data in eeprom entry. when the ? en_osd ? is active high, the osd is active, and the SD1200 will send the osd data to the lcd panel. the osd has 16 different color schemes based on the combinations of the three osd color pins and the ? osd intensity ? data. when r_osd=1, and osd_intensity=0, the SD1200 will output 128 to the output red channel, r_out. when r_osd=1, and osd_intensity=1, the SD1200 will output 255. the same scheme is used for g_osd to g_out and for b_osd to b_out. 3.4.2. lcd interface the SD1200 support 48-bit rgb interface with xga/sxga lcd panels from various panel manufacturers. the lcd panel resolution and timing information is stored in the external eeprom. the information in the eeprom includes timing related to the output back porch, synchronization pulse width and valid data window. the timing information is used to generate the frequency divider for the output pll, to lock the pll output clock with hsync for the lcd data clock, and to synchronized the output vsync and input vsync.
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 20 3.5. eeprom interface as mentioned in previous sections, the external eeprom stores much crucial information for the SD1200 internal operations. the SD1200 interfaces with the eeprom through a 2-wire i 2 c serial interface. the suggested eeprom device is an industry standard serial-interface eeprom (24x08). the i 2 c interface scheme is briefly described here and detail description can be found in many public literatures. 3.5.1. i 2 c serial interface the i 2 c serial interface used 2 wires, scl and sda. the scl is driven by the SD1200, and used mainly as the sampling clock and the sda is a bi-directional signal and used mainly for data signal. figure 4 shows the basic bit definitions of i 2 c serial interface. the i 2 c serial interface supports random read and sequential read operations. figure 5 and 6 shows the data sequences for random read and sequential read operations. figure 4: start, stop and data definitions in i 2 c serial interface start stop data change data stable data change
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 21 figure 5: data sequence for single byte random access s t a r t r e a d word address [5:0] device address [6:0] l s b b i t 0 m s b b i t r /_ w a c k l s b b i t 0 m s b b i t a c k s t o p a c k data l s b b i t 0 m s b b i t
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 22 figure 6: data sequence for multiple byte sequential access s t o p data n a c k l s b b i t 0 m s b b i t 7 a c k data n+x l s b b i t 0 m s b b i t 7 a c k s t a r t r e a d word address [5:0] device address [6:0] l s b b i t 0 m s b b i t 6 r /_ w a c k m s b b i t 7
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 23 3.5.2. eeprom contents the contents of eeprom are primarily dependent on the specifications of the lcd panel. smartasic provides suggested eeprom contents for lcd panels from various panel manufacturers. the section presents all the entries in the eeprom, and briefly describes their definitions. that allows the system manufacturers to have their own eeprom contents to distinguish their monitors. the eeprom contents can be partitioned into 11 parts. the first 8 parts are input mode dependent. when the SD1200 detects the input mode, it will then load the information related to the detected mode from the eeprom. the information in the 9 th part is mainly for input mode detection as well as some threshold values for error status indicators. the 10 th and 11 th parts are look up table for interpolation parameters. the 9 th , 10 th and 11 th parts are loaded in the SD1200 during the reset time. part 1: 640x350 mode, part 2: 640x400 mode, part 3: 720x400 mode, part 4: 640x480 mode, part 5: 800x600 mode, part 6: 1024x768 mode, part 7: 1280x1024 mode, and part 8: user defined mode part 9: input mode detection and scaling related parameters part 10: lookup table for horizontal interpolation part 11: lookup table for vertical interpolation
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 24 part 1-8: input mode dependent data symbol w 640 x 350 640 x 400 720 x 400 640 x 480 800 x 600 1024 x 768 1280 x 1024 inv ali d description vpw 11 00h 01h 20h 21h 40h 41h 60h 61h 80h 81h a0h a1h c0h c1h e0h e1h lcd vsync pulse width vbp 11 02h 03h 22h 23h 42h 43h 62h 63h 82h 83h a2h a3h c2h c3h e2h e3h lcd vsync back porch (including vpw) vbp source 11 04h 05h 24h 25h 44h 45h 64h 65h 84h 85h a4h a5h c4h c5h e4h e5h lcd vsync back porch (source equivalent) = vbp * line expansion and round up target skip pixel 11 06h 07h 26h 27h 46h 47h 66h 67h 86h 87h a6h a7h c6h c7h e6h e7h if vbp can not be converted into source evenly, the leftover is converted into number of pixels vsize 11 08h 09h 28h 29h 48h 49h 68h 69h 88h 89h a8h a9h c8h c9h e8h e9h lcd number of lines hpw 11 0ah 0bh 2ah 2bh 4ah 4bh 6ah 6bh 8ah 8bh aah abh cah cbh eah ebh lcd hsync pulse width hbp 11 0ch 0dh 2ch 2dh 4ch 4dh 6ch 6dh 8ch 8dh ach adh cch cdh ech edh lcd hsync back porch(including hpw) hsize 11 0eh 0fh 2eh 2fh 4eh 4fh 6eh 6fh 8eh 8fh aeh afh ceh cfh eeh efh lcd number of columns htotal 11 10h 11h 30h 31h 50h 51h 70h 71h 90h 91h b0h b1h d0h d1h f0h f1h lcd total number of pixels per line including all porches htotal source 12 12h 13h 32h 33h 52h 53h 72h 73h 92h 93h b2h b3h d2h d3h f2h f3h lcd total number of clocks per line (source equivalent) = htotal/line expansion line expansion 4 14h [6:3] 34h [6:3] 54h [6:3] 74h [6:3] 94h [6:3] b4h [6:3] d4h [6:3] f4h [6:3] vertical source to destination scaling factor 0: 1 to 1 1: 2 to 3 2: 3 to 4 3: 5 to 8 4: 15 to 32 5: 25 to 32 6: 25 to 48 7: 25 to 64 8: 75 to 128 9: 175 to 384 10: 175 to 512 pixel expansion 3 14h [2:0] 34h [2:0] 54h [2:0] 74h [2:0] 94h [2:0] b4h [2:0] d4h [2:0] f4h [2:0] horizontal source to destination scaling factor 0: 1 to 1 1: 2 to 4 2: 4 to 5 3: 25 to 36 4: 5 to 8 5: 9 to 10 6: 45 to 64 7: 9 to 16
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 25 fog factor horizontal 8 15h 35h 55h 75h 95h b5h d5h f5h horizontal fogging factor fog factor 2x 8 16h 36h 56h 76h 96h b6h d6h f6h double of horizontal fogging factor fog factor vertical 8 17h 37h 57h 77h 97h b7h d7h f7h vertical fogging factor minimum input lines 11 18h 19h 38h 39h 58h 59h 78h 79h 98h 99h b8h b9h d8h d9h f8h f9h minimum input lines = (vsize + vbp)* line expansion when the input has fewer lines than this value, it is considered as an error, and input_x status bit will be high. maximum input pixels 11 1ah 1bh 3ah 3bh 5ah 1bh 7ah 7bh 9ah 9bh bah bbh dah dbh fah fbh maximum input pixels per line. auto clock recovery will not set input pll divisor larger than this value. source hsize[11:8] 3 1ch [6:4] 3ch [6:4] 5ch [6:4] 7ch [6:4] 9ch [6:4] bch [6:4] dch [6:4] fch [6:4] source horizontal size upper 3 bits source vsize[11:8] 3 1ch [2:0] 3ch [2:0] 5ch [2:0] 7ch [2:0] 9ch [2:0] bch [2:0] dch [2:0] fch [2:0] source vertical size upper 3 bits source hsize[7:0] 8 1dh 3dh 5dh 7dh 9dh bdh ddh fdh source horizontal size lower 8 bits source vsize[7:0] 8 1eh 3eh 5eh 7eh 9eh beh deh feh source vertical size lower 8 bits check sum 8 1fh 3fh 5fh 7fh 9fh bfh dfh ffh sum of above 31 bytes (keep lower 8 bits only) part 9: input mode detection data symbol width (bits) address description data low threshold 8 120h low water mark for valid data if the data is smaller than this threshold, it is considered low internally data high threshold 8 121h high water mark for valid data if the data is larger than this threshold, it is considered high internally edge threshold 8 122h minimum difference between the data value of two adjacent pixels to be considered as an edge calibration mode 2 123h [1:0] this is to select different operation modes of internal phase calibration. the selection criterion is as follow: 0: when input video signal has large overshot, it results in longest calibration time 1: when input video signal has median overshot, it results in long calibration time 2: when input video signal has normal overshot, it results in normal calibration time (recommended) 3: when input video signal has no overshot, it results in shortest calibration time res0 threshold 10 124h-125h upper bound of the line number for 640x350 mode, and lower bound for 640x400 res1 threshold 10 126h-127h upper bound of the line number for 640x400 mode,
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 26 and lower bound for 720x400 res2 threshold 10 128h-129h upper bound of the line number for 720x400 mode, and lower bound for 640x480 res3 threshold 10 12ah-12bh upper bound of the line number for 640x480 mode, and lower bound for 800x600 res4 threshold 10 12ch-12dh upper bound of the line number for 800x600 mode, and lower bound for 1024x768 res5 threshold 10 12eh-12fh upper bound of the line number for 1024x768 mode, and lower bound for 1280x1024 res6 threshold 10 130h-131h upper bound of the line number for 1280x1024 mode. if the input has more line than this threshold, it is considered invalid mode mode 640x350 sync polarity 2 132h[1:0] the polarity of input synchronization signals bit 0 is for vsync and bit 1 is for hsync mode 640x400 sync polarity 2 132h[3:2] the polarity of input synchronization signals bit 0 is for vsync and bit 1 is for hsync mode 720x400 sync polarity 2 132h[5:4] the polarity of input synchronization signals bit 0 is for vsync and bit 1 is for hsync mode 640x480 sync polarity 2 132h[7:6] the polarity of input synchronization signals bit 0 is for vsync and bit 1 is for hsync mode 800x600 sync polarity 2 133h[1:0] the polarity of input synchronization signals bit 0 is for vsync and bit 1 is for hsync mode 1024x768 sync polarity 2 133h[3:2] the polarity of input synchronization signals bit 0 is for vsync and bit 1 is for hsync mode 1280x1024 sync polarity 2 133h[5:4] the polarity of input synchronization signals bit 0 is for vsync and bit 1 is for hsync maximum vbp 8 134h the maximum vertical back porch for input video pwm unit delay 13 135h-136h the unit delay used in the external pwm delay circuitry. if the free-running clock is 1mhz, and the intended unit delay is 0.2 ns (= 5,000mhz), then a value of 5,000mhz/1mhz = 5,000 is used here. maximum link off time 22 137h-139h maximum time when input vsync is off before the link_dwn pin turns on (unit: clock period of the free running clock). if the free-running clock is 1mhz, and the intended maximum time is 1 second, then a value of 1,000,000 us/ 1 us = 1,000,000 is used here. maximum refresh rate 16 13ah-13bh maximum refresh rate supported by the lcd panel if the intended maximum refresh rate is 75hz, and the free-running clock is 1mhz, then a value of 1000000/75=133,333 is used here maximum input frequency 8 13ch maximum source clock rate supported by the SD1200 (unit: frequency of free-running clock) if the intended maximum clock rate is 60mhz, and the free-running clock is 1mhz, then a value of 60 is used here. if the input signal has a higher frequency than this value, the vclk0_x status bit will turn on. scale factor ce 8 13dh scale factor used when generate look up table for current even pixel multiplication scale factor co 8 13eh scale factor used when generate look up table for current odd pixel multiplication scale factor ne 8 13fh scale factor used when generate look up table for next even pixel multiplication
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 27 scale factor no 8 140h scale factor used when generate look up table for next odd pixel multiplication offset factor ce 8 141h offset factor used when generate look up table for current even pixel multiplication offset factor co 8 142h offset factor used when generate look up table for current odd pixel multiplication offset factor ne 8 143h offset factor used when generate look up table for next even pixel multiplication offset factor no 8 144h offset factor used when generate look up table for next odd pixel multiplication scale factor v 8 145h scale factor used when generate look up table for line multiplication offset factor v 8 146h offset factor used when generate look up table for line multiplication minimum pixels per line for lcd 11 147h-148h minimum number of pixels per line for lcd panel lcd polarity 4 149h[3:0] controls the polarity of output vsync, hsync, clock and display enable bit0: 0: clock active high, 1: clock active low bit1: 0: hsync active low, 1: hsync active high bit2: 0: vsync active low, 1: vsync active high bit4: 0: de active high, 1: de active low check sum 8 14ah sum of all part 9 bytes (keep only lower 8 bit) part 10: horizontal interpolation lookup table symbol width (bits) address description mapped value 8 1c0h-2bfh this is the base table for all four horizontal interpolation lookup tables. each table is then generated by multiply this value with corresponding scale factor and added with corresponding offset factor. check sum 8 2c0h sum of all part 10 entry (only keep lower 8 bits) part 11: vertical interpolation lookup table symbol width (bits) address description mapped value 8 2e0h-3dfh this is the base table for vertical interpolation lookup table. the vertical interpolation table is then generated by multiply this value with vertical scale factor and added with vertical offset factor. check sum 8 3e0h sum of all part 10 entry (only keep lower 8 bits)
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 28 3.6. cpu interface the SD1200 supports 2-wire i 2 c serial interface to external cpu. the interface allows external cpu to access and modify control registers inside the SD1200. the i 2 c serial interface is similar to the eeprom interface, and the cpu is the host that drives the scl all the time as the clock and for ? start ? and ? stop ? bits. the scl frequency can be as high as 5mhz. the sda is a bi-directional data wire. this interface supports random and sequential write operations for cpu to modify one or multiple control registers, and random and sequential read operations for cpu to read all or part of the control registers. the lower 4 bits of device id for SD1200 are fixed at ? 1010 ? . the upper 3 bits are programmable through mode_in3 (pin 19), mode_in2 (pin 18) and mode_in1 (pin 15). this avoids any conflict with other i2c devices on the same bus. the following table briefly describes the SD1200 control registers. external cpu can read these register to know the state of the SD1200 as well as the result of input mode detection and phase calibration. external cpu can modify these control registers to disable several SD1200 features and force the SD1200 into a particular state. when the cpu modifies the control registers, the new data will be first stored in a set of shadow registers, and then are copied into the actual control registers when the ? cpu control enable ? bit is set. when the ? cpu control enable ? bit is set, the external cpu will retain control and the SD1200 will not perform the auto mode detection and auto calibration. the external cpu is able to adjust the size of the output image and move the output image up and down by simply changing the porch size and pixel and line numbers of the input signal. these adjustments can be tied to the external user control button on the monitor. a set of four control registers are used to generate output signal when there is no input signal available to the SD1200, or the input signal is beyond the acceptable ranges. this operation mode is called standalone mode, which is very important for the end users when they accidentally select an input mode beyond the acceptable range of the SD1200, or when the input cable connection becomes loose for any reason. system
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 29 manufacturers can display appropriate osd warning messages on the lcd panel to notify the users about the problem. table 3: SD1200 control registers symbol width mode address description vbp source 11 rw 0h-1h input vsync back porch (not include pulse width) vsize source 11 rw 2h-3h input image lines per frame vtotal source 11 rw 4h-5h input total number of lines including porches hbp source 11 rw 6h-7h input hsync back porch (not include pulse width) hsize source 11 rw 8h-9h input image pixels per line htotal source 11 rw ah-bh input total number of pixels per line including porches mode source 3 rw ch[2:0] input video format 0: 640x350 1: 640x400 2: 720x400 3: 640x480 4: 800x600 5: 1024x768 6: 1280x1024 7: invalid clock phase source 9 rw dh-eh input sampling clock phase vpw standalone 10 rw fh-10h for standalone mode, the pulse width of vsync vtotal standalone 10 rw 11h-12h for standalone mode, total number of line per frame hpw standalone 10 rw 13h-14h for standalone mode, hsync active time in us htotal standalone 10 rw 15h-16h for standalone mode, hsync cycle time in us disable auto calibration for mode 640x350 1 rw 17h[7] disable auto calibration for this mode 1: disable 0: enable delay auto calibration for mode 640x350 15 rw 17h[6:0]- 18h the number of frames need to be skipped before starting auto calibration for this mode disable auto calibration for mode 640x400 1 rw 19h[7] disable auto calibration for this mode 1: disable 0: enable delay auto calibration for mode 640x400 15 rw 19h[6:0]- 1ah the number of frames need to be skipped before starting auto calibration for this mode disable auto calibration for mode 720x400 1 rw 1bh[7] disable auto calibration for this mode 1: disable 0: enable delay auto calibration for mode 720x400 15 rw 1bh[6:0]- 1ch the number of frames need to be skipped before starting auto calibration for this mode disable auto calibration for mode 640x480 1 rw 1dh[7] disable auto calibration for this mode 1: disable 0: enable delay auto calibration for mode 640x480 15 rw 1dh[6:0]- 1eh the number of frames need to be skipped before starting auto calibration for this mode
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 30 disable auto calibration for mode 800x600 1 rw 1fh[7] disable auto calibration for this mode 1: disable 0: enable delay auto calibration for mode 800x600 15 rw 1fh[6:0]- 20h the number of frames need to be skipped before starting auto calibration for this mode disable auto calibration for mode 1024x768 1 rw 21h[7] disable auto calibration for this mode 1: disable 0: enable delay auto calibration for mode 1024x768 15 rw 21h[6:0]- 22h the number of frames need to be skipped before starting auto calibration for this mode disable auto calibration for mode 1280x1024 1 rw 23h[7] disable auto calibration for this mode 1: disable 0: enable delay auto calibration for mode 1280x1024 15 rw 23h[6:0]- 24h the number of frames need to be skipped before starting auto calibration for this mode disable auto calibration for mode invalid 1 rw 25h[7] disable auto calibration for this mode 1: disable 0: enable delay auto calibration for mode invalid 15 rw 25[6:0]- 26h the number of frames need to be skipped before starting auto calibration for this mode bypass sync polarity 1 rw 27h[7] bypass input sync polarity detection (default 0) 1: bypass input sync polarity detection 0: detect input sync polarity and make them negative polarity enable sync check 7 rw 27h[6:0] enable sync polarity check during input mode detection (default all 0). 1: enable sync polarity based mode detection 0: disable sync polarity based mode detection bit 0: 640x350 bit 1: 640x400 bit 2: 720x400 bit 3: 640x480 bit 4: 800x600 bit 5: 1024x768 bit 6: 1280x1024 dithering enable 1 rw 28h[7] enable dithering for 6 bit panel (default 0) 1: enable dithering 0: disable dithering frame modulation enable 1 rw 28h[6] enable frame modulation for 6 bit panel (default 0) 1: enable frame modulation 0: disable frame modulation horizontal interpolation enable 1 rw 28h[5] enable horizontal interpolation (default 0) 1: enable horizontal interpolation 0: disable horizontal interpolation vertical interpolation enable 1 rw 28h[4] enable vertical interpolation (default 0) 1: enable vertical interpolation 0: disable vertical interpolation horizontal rounding enable 1 rw 28h[3] enable horizontal rounding (default 0) 1: enable horizontal rounding 0: disable horizontal rounding vertical rounding enable 1 rw 28h[2] enable vertical rounding (default 0) 1: enable vertical rounding 0: disable vertical rounding horizontal table 1 rw 28h[1] enable horizontal table lookup (default 0)
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 31 lookup enable 1: enable horizontal table lookup 0: disable horizontal table lookup vertical table lookup enable 1 rw 28h[0] enable vertical table lookup (default 0) 1: enable vertical table lookup 0: disable vertical table lookup hsync threshold enable 1 rw 29h[4] enable detection of short lines (ibm panel only, default 0) 1: enable such detection 0: disable such detection osd intensity 1 rw 29h[3] osd intensity selection 0: half intensity 1: full intensity load all eeprom 1 rw 29h[2] should be kept low most time. a high pulse will force SD1200 to reload all eeprom entries load mode dependent eeprom 1 rw 29h[1] should be kept low most time. a high pulse will force SD1200 to reload mode dependent eeprom entries cpu control enable 1 rw 29h[0] external cpu control enable 0: disable external cpu control. SD1200 can write control registers, but cpu only read control registers. 1: enable external cpu control. cpu can read/write control registers. SD1200 cannot write control registers status 0 8 r 2ah read only internal status registers 1: indicate error status 0: indicate normal status bit 0: eeprom vertical lookup table loading bit 1: eerpom horizontal lookup table loading bit 2: eeprom mode dependent entries loading bit 3: eeprom calibration entries loading bit 4: input has too few lines bit 5: no input video bit 6: input data clock is too fast bit 7: refresh rate exceed lcd panel specification status 1 4 r 2bh[3:0] internal auto calibration state
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 32 4. electrical specification this section presents the electrical specifications of the SD1200. 4.1. absolute maximum ratings symbol parameter rating units vcc power supply -0.3 to 6.0 v vin input voltage -0.3 to vcc + 0.3 v vout output voltage -0.3 to vcc +0.3 v tstg storage temperature -55 to 150 c 4.2. recommended operating conditions symbol parameter min. typ. max. units vcc commercial power supply 4.75 5.0 5.25 v vcc industrial power supply 4.5 5.0 5.5 v vin input voltage 0 - vcc v tj commercial junction operating temperature 0 25 115 c tj industrial junction operating temperature -40 25 125 c 4.3. general dc characteristics symbol parameter conditions min. typ. max. units iil input leakage current no pull ? up or pull - down -1 1 m a ioz tri-state leakage current -10 10 m a cin input capacitance 3 r f cout output capacitance 3 r f cbid3 bi-directional buffer capacitance 3 r f note: the capacitance above does not include pad capacitance and package capacitance. one can estimate pin capacitance by adding pad capacitance, which is about 0.5 r f and the package capacitance
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 33 4.4. dc electrical characteristics for 3.3 v operation (under recommended operation conditions and v cc = 3.0 ~ 3.6v, t j = 0 c to +115 c) symbol parameter conditions min. typ. max. units vil input low voltage cmos 0.3*vcc v vih input high voltage cmos 0.7*vcc v vt- schmitt trigger negative going threshold voltage coms 1.22 v vt+ schmitt trigger positive going threshold voltage coms 2.08 v vol output low voltage ioh=2,4,8,12, 16,24 ma 0.4 v voh output high voltage ioh=2,4,8,12, 16,24 ma 2.4 v ri input pull-up /down resistance vil=0v or vih=vcc 75 k w 4.5. dc electrical characteristics for 5v operation (under recommended operation conditions and v cc =4.75~5.25,t j =0 c to +115 c) symbol parameter conditions min. typ. max. units vil input low voltage coms 0.3*vcc v vih input high voltage coms 0.7*vcc v vil input low voltage ttl 0.8 v vih input high voltage ttl 2.0 v vt- schmitt trigger negative going threshold voltage cmos 1.84 v vt+ schmitt trigger positive going threshold voltage coms 3.22 v vt- schmitt trigger negative going threshold voltage ttl 1.10 v vt+ schmitt trigger positive going threshold voltage ttl 1.87 v vol output low voltage iol=2,4,8,16,24ma 0.4 v voh output high voltage ioh=2,4,8,16,24 ma 3.5 v ri input pull-up / down resistance vil=0v or vih=vcc 50 k w
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 34 5. package dimensions
smartasic, inc. SD1200 preliminary data sheet september, 1998 smartasic confidential 35 6. order information order code temperature package speed SD1200 commercial 0 c ~ 70 c 160-pin pqfp 14 x 20 (mm) 60mhz smartasic , inc. worldwide office u.s.a. (headquarter) asia pacific 2674 n. first street, suite 112 13f, no. 11, chung- shan n. rd. san jose, ca 95134 u.s.a. taipei, taiwan r.o.c. tel : 1-408-383-1818 tel : 886-2-2542-5169 fax : 1-408-383-1819 fax : 886-2-2542-5166 @copyright 1998, smartasic, inc. this information in this document is subject to change without notice. smartasic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. smartasic does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications.

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